512k x 24 static ram module cym8301bv33 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-05294 rev. ** revised may 13, 2002 features ? high-density 12-megabit sram module access time: 10 ns single 3.3v power supply low active power(1000 w max.) ttl-compatible inputs and outputs available in standard 119-ball bga interface to motorola digital signal processor (dsp) and analog devices functional description the cym8301bv33 is a 3.3v high-performance 12-megabit static ram organized as a 512k words by 24 bits. this module is constructed from three 512k 8 sram dice mounted on a multi layer laminate substrate combined to form a 24 bit sram. cym8301bv33 is a ideal single-chip solution for motorola ? s dsp5630x or a two chip solution to analog devices adsp2106xl. each data byte is separately controlled by the individual chip selects(ce0 ,ce1 ,ce2 ). ce0 controls i/o0 ? 7. ce1 controls i/o7 ? 15. ce2 controls i/o16 ? 23. writing the data bytes into the sram is accomplished when the chip select (cs x) controlling that byte is low and write enable (we ) is low.data on the respective input/output pins (i/o) is then written into the memory location specified on the address pins (a0 through a18). asserting all the (cs x) low and (we ) low will write the entire data (i/o0 ? 23) into the memory. output enable (oe ) is a don ? t care in a write mode. reading a byte is accomplished when the chip select (cs x) controlling that byte is low and write enable (we ) is low while the output enable (oe ) is low.under these conditions the contents of the memory location specified on the address pins will all appear on the specified data input/output pins (i/o). asserting all the (cs x) low and (we ) low with output enable (oe ) low will read the entire data (i/o0-23) from the memory. the data input/output pins (i/o0 ? 23) are placed in a high-impedance state when the device is deselected (ce ) high, the outputs are disabled (oe ) high or during a write operation (ce low, and we low). for further details on read and write conditions, please see the truth table on page 7 of this data sheet. selection guide cym8301bv33-10 cym8301bv33-12 cym8301bv33-15 unit maximum access time 10 12 15 ns maximum operating current commercial 300 270 255 ma industrial 330 300 285 maximum standby current commercial/industrial 30 30 30 ma functional block diagram a[18:0] we oe ce0 ce1 ce2 i/o0 ? 23 i/o0 ? 7 i/o8 ? 15 i/o16 ? 23 i/o0 ? 7 i/o0 ? 7 i/o0 ? 7 ce a[18:0] a[18:0] a[18:0] ce ce we oe oe oe we we 8 8 8
cym8301bv33 document #: 38-05294 rev. ** page 2 of 9 pin configurations 119 bga top view 1234567 a nc a a a a a nc b nc a a ce0 aanc c i/o12 nc ce1 nc ce2 nc i/o0 d i/o13 v dd v ss v ss v ss v dd i/o1 e i/o14 v ss v dd v ss v dd v ss i/o2 f i/o15 v dd v ss v ss v ss v dd i/03 g i/o16 v ss v dd v ss v dd v ss i/04 h i/o17 v dd v ss v ss v ss v dd i/o5 j nc v ss v dd v ss v dd v ss nc k i/o18 v dd v ss v ss v ss v dd i/o6 l i/o19 v ss v dd v ss v dd v ss i/o7 m i/o20 v dd v ss v ss v ss v dd i/o8 n i/o21 v ss v dd v ss v dd v ss i/09 p i/o22 v dd v ss v ss v ss v dd i/o10 r i/o23 a nc nc nc a i/o11 t nc a a we aanc u nc a a oe aanc
cym8301bv33 document #: 38-05294 rev. ** page 3 of 9 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied............................................. ? 55 c to +125 c supply voltage on v cc to relative gnd [1] ...... ? 0.5v to 4.6v dc voltage applied to outputs in high-z state [1] .................................... ? 0.5v to v cc + 0.5v dc input voltage [1] ................................. ? 0.5v to v cc + 0.5v current into outputs (low)......................................... 20 ma static discharge voltage .......................................... > 2001v (per mil-std-883, method 3015) latch-up current..................................................... > 200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 3.3v 5% industrial ? 40 c to +85 c 3.3v 5% electrical characteristics over the operating range parameter description test conditions [2] cym8301bv33-10 cym8301bv33-12/15 unit min. max. min. max. v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v il input low voltage [1] ? 0.5 0.8 ? 0.5 0.8 v i ix input load current gnd < v i < v cc ? 10 +10 ? 10 +10 a i oz output leakage current gnd < v i < v cc , output disabled ? 10 +10 ? 10 +10 a i cc v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 300 300 ma i sb1 automatic ce power-down current ? ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max 150 150 ma i sb2 automatic ce power-down current ? cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 30 30 ma capacitance [3] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 8pf c out output capacitance 8 pf notes: 1. v il (min.) = ? 2.0v for pulse durations of less than 20 ns. 2. ce is a combination of ce1 , ce2 and ce3 . 3. tested initially and after any design or process changes that may affect these parameters.
cym8301bv33 document #: 38-05294 rev. ** page 4 of 9 ac test loads and waveforms 90% 10% 3.0v gnd 90% 10% all input pulses 3.3v output 5 pf including jig and scope (a) (b) 3 ns 3ns r1 317 ? r2 351 ? output r l = 50 ? z 0 = 50 ? v th = 1.5v switching characteristics [4] over the operating range parameter description [2] cym8301bv-10 cym8301bv-12 cym8301bv-15 unit min. max. min. max. min. max. read cycle t rc read cycle time 10 12 15 ns t aa address to data valid 10 12 15 ns t oha data hold from address change 3 3 3 ns t ace ce active to data valid 10 12 15 ns t doe oe low to data valid 7 7.5 8.5 ns t lzoe oe low to low-z 0 0 0 ns t hzoe oe high to high-z [5, 6] 567ns t lzce ce active to low-z [6] 333ns t hzce ce inactive to high-z [5, 6] 567ns t pu ce active to power-up 0 0 0 ns t pd ce inactive to power-down 10 12 15 ns write cycle [7, 8] t wc write cycle time 10 12 15 ns t sce ce active to write end 9 9 9 ns t aw address set-up to write end 9 9 10 ns t ha address hold from write end 0 0 0 ns t sa address set-up to write start 0 0 0 ns t pwe we pulse width 8 10 11 ns t sd data set-up to write end 6 6 7 ns t hd data hold from write end 0 0 0 ns t lzwe we high to low-z [6] 333ns t hzwe we low to high-z [5, 6] 567ns notes: 4. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh . 5. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-state voltage. 6. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 7. the internal write time of the memory is defined by the overlap of ce low and we low. ce and we must be low to initiate a write, and the transition of any of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the si gnal that terminates the write. 8. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd .
cym8301bv33 document #: 38-05294 rev. ** page 5 of 9 switching waveforms read cycle no. 1 [9, 10] read cycle no. 2 (oe controlled) [2, 10, 11] write cycle no. 1 (ce controlled) [2, 12, 13] notes: 9. device is continuously selected. oe , ce = v il . 10. we is high for read cycle. 11. address valid prior to or coincident with ce transition low. 12. data i/o is high impedance if oe = v ih . 13. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce i cc i sb impedance address data out v cc supply current t wc data valid t aw t sa t pwe t ha t hd t sd t sce t sce ce address we data i/o
cym8301bv33 document #: 38-05294 rev. ** page 6 of 9 write cycle no. 2 (we controlled, oe high during write) [12, 13] write cycle no. 3 (we controlled, oe low) [2, 13] note: 14. during this period the i/os are in the output state and input signals should not be applied. switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 14 data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 14
cym8301bv33 document #: 38-05294 rev. ** page 7 of 9 truth table ce1 ce2 ce3 we oe i/o 0 ? i/o 23 mode h h h x x high-z deselect/power-down l l l h l data out (i/o0 ? 23) read l l l h h i/o high-z power-down l h h h l data out (i/o0 ? 7) i/o8-23 in high-z read h l h h l data out (i/o8 ? 15) i/o0 ? 7 in high-z i/o16 ? 23 in high-z read h h l h l data out (i/o16 ? 23) i/o0 ? 15 in high-z read l l l l x data in (i/o0 ? 23) write l h h l x data in (i/o0 ? 7) write h l h l x data in (i/o8 ? 15) write h h l l x data in (i/o16 ? 23) write ordering information speed (ns) ordering code package name package type operating range 10 cym8301bv33 - 10bgc bg119 119-ball bga commercial cym8301bv33 - 10bgi bg119 119-ball bga industrial 12 cym8301bv33 - 12bgc bg119 119-ball bga commercial cym8301bv33 - 12bgi bg119 119-ball bga industrial 15 cym8301bv33 - 15bgc bg119 119-ball bga commercial cym8301bv33 - 15bgi bg119 119-ball bga industrial
cym8301bv33 document #: 38-05294 rev. ** page 8 of 9 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagram all product and company names mentioned in this document are the trademarks of their respective holders. 119-ball pbga (14 x 22 x 2.4 mm) bg119 51-85115-*a
cym8301bv33 document #: 38-05294 rev. ** page 9 of 9 document title: cym8301bv33 512k x 24 static ram module document number: 38-05294 rev. ecn no. issue date orig. of change description of change ** 114945 05/20/02 dfp new data sheet
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